The next generation high performance opto-electronic systems are known to need about a ten-fold increase in interconnection bandwidth about every four years. Against this increase in demand are the requirements to maintain cost, power and space as minimal as possible. Moore's Law and the newer 2.5D/3D IC packaging technologies have enabled a degree of integration advances sufficient to address most of the interconnection bandwidth concerns. However, this improvement has been achieved at an extremely high cost, and often with high power demands and/or the need for relatively large-sized configurations for all of the requisite electrical and optical interconnections.
While advances in silicon photonics is expected to play a key role in addressing some of these goals, inasmuch as it allows for integration to keep pace with Moore's Law and minimizes some costs by taking advantage of well-known IC fabrication techniques, there remains many concerns regarding optimum configurations for packaging these interconnection components, particularly configurations scalable with proposed large numbers of high bandwidth interconnects for next generation systems.